用verilog写的(7,3)循环码编码

上传者: xinglinhai1972 | 上传时间: 2019-12-21 22:03:35 | 文件大小: 37KB | 文件类型: zip
我自己原创的用verilog hdl语言编写的一个(7,3)循环码的编码器.文件压缩包中除了有.v的源文件外,还把在maxplusII下仿真波形图的文件也包括进去了,供网友参考.仿真中输入了两个信息码字分别是"011"和"101".生成多项式采用的是x^4+x^3+x^2+1

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评论信息

  • Jody1989 :
    初学者参考
    2015-05-11
  • haotoupi :
    很好,可以编译
    2015-01-03

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