基于FPGA的红外收发代码

[{"title":"（ 34 个子文件 356KB ） 基于FPGA的红外收发代码","children":[{"title":"16","children":[{"title":"IrDA.bdf <span style='color:#111;'> 12.38KB </span>","children":null,"spread":false},{"title":"jk_ff.bsf <span style='color:#111;'> 2.06KB </span>","children":null,"spread":false},{"title":"IrDAnios.bsf <span style='color:#111;'> 1.25KB </span>","children":null,"spread":false},{"title":"IrDA_TOP.bdf <span style='color:#111;'> 16.33KB </span>","children":null,"spread":false},{"title":"reset_counter.bsf <span style='color:#111;'> 3.24KB </span>","children":null,"spread":false},{"title":"Verilog HDL Files","children":[{"title":"onchip_memory2_0.v <span style='color:#111;'> 3.68KB </span>","children":null,"spread":false},{"title":"cpu_0_jtag_debug_module_tck.v <span style='color:#111;'> 7.81KB </span>","children":null,"spread":false},{"title":"UART.V <span style='color:#111;'> 1.50KB </span>","children":null,"spread":false},{"title":"Uart_tb.v <span style='color:#111;'> 1.90KB </span>","children":null,"spread":false},{"title":"epcs_flash_controller_0.v <span style='color:#111;'> 17.80KB </span>","children":null,"spread":false},{"title":"reset_counter.v <span style='color:#111;'> 4.40KB </span>","children":null,"spread":false},{"title":"cpu_0_oci_test_bench.v <span style='color:#111;'> 1.31KB </span>","children":null,"spread":false},{"title":"cpu_0_test_bench.v <span style='color:#111;'> 27.77KB </span>","children":null,"spread":false},{"title":"IrDAnios_inst.v <span style='color:#111;'> 296B </span>","children":null,"spread":false},{"title":"cpu_0.v <span style='color:#111;'> 285.88KB </span>","children":null,"spread":false},{"title":"cpu_0_mult_cell.v <span style='color:#111;'> 5.98KB </span>","children":null,"spread":false},{"title":"irda_uart_tb.v <span style='color:#111;'> 2.12KB </span>","children":null,"spread":false},{"title":"PLL.v <span style='color:#111;'> 14.23KB </span>","children":null,"spread":false},{"title":"IrDAnios.v <span style='color:#111;'> 203.72KB </span>","children":null,"spread":false},{"title":"irda_uart.v <span style='color:#111;'> 1.19KB </span>","children":null,"spread":false},{"title":"Status.v <span style='color:#111;'> 1.77KB </span>","children":null,"spread":false},{"title":"receiver.v <span style='color:#111;'> 4.38KB </span>","children":null,"spread":false},{"title":"jtag_uart_0.v <span style='color:#111;'> 22.16KB </span>","children":null,"spread":false},{"title":"transmit.v <span style='color:#111;'> 3.39KB </span>","children":null,"spread":false},{"title":"RW_Ctr.v <span style='color:#111;'> 2.05KB </span>","children":null,"spread":false},{"title":"cpu_0_jtag_debug_module_wrapper.v <span style='color:#111;'> 9.22KB </span>","children":null,"spread":false},{"title":"IrDA_DATABus.v <span style='color:#111;'> 2.38KB </span>","children":null,"spread":false},{"title":"irendec.v <span style='color:#111;'> 2.97KB </span>","children":null,"spread":false},{"title":"cpu_0_jtag_debug_module_sysclk.v <span style='color:#111;'> 6.62KB </span>","children":null,"spread":false}],"spread":false},{"title":"irda_uart.bsf <span style='color:#111;'> 3.43KB </span>","children":null,"spread":false},{"title":"PLL.bsf <span style='color:#111;'> 2.92KB </span>","children":null,"spread":false},{"title":"irendec.bsf <span style='color:#111;'> 2.27KB </span>","children":null,"spread":false},{"title":"delay_reset_block.bdf <span style='color:#111;'> 8.34KB </span>","children":null,"spread":false},{"title":"delay_reset_block.bsf <span style='color:#111;'> 2.54KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]