Verilog实现96路信号正交调制解调，通过Quartus实现，含有完整仿真文件

[{"title":"（ 538 个子文件 146.17MB ） Verilog实现96路信号正交调制解调，通过Quartus实现，含有完整仿真文件","children":[{"title":"ori_M.jpg <span style='color:#111;'> 90.60KB </span>","children":null,"spread":false},{"title":"sink_sop_eop.png <span style='color:#111;'> 23.57KB </span>","children":null,"spread":false},{"title":"ori_V.png <span style='color:#111;'> 39.43KB </span>","children":null,"spread":false},{"title":"de_V.png <span style='color:#111;'> 29.98KB </span>","children":null,"spread":false},{"title":"信号.png <span style='color:#111;'> 35.36KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]